Reductions in the minimum lithographic dimension of integrated circuit fabrication processes have made the space required for linear capacitors disproportionately large relative to other circuit components. The following background is provided to more thoroughly describe this problem.
Capacitors are used extensively in integrated circuits. Linear capacitors with small voltage dependence are essential in many applications including analog to digital and digital to analog converters, sample and holds and phase locked loops. A capacitor is linear if the value of the capacitance does not depend on voltage. The cost of an integrated circuit for a given manufacturing process is directly related to the size of the integrated circuit die. In recent years a wide range of technological developments have been made to reduce the minimum lithographic dimension of integrated circuits. An important feature of a capacitor is its quality factor, Q. Q is inversely proportional to the series resistance of a capacitor, and is therefore a measure of the quality of a capacitor.
Traditionally three different types of capacitors are used in integrated circuits: junction capacitors, metal-oxide-semiconductor (MOS) capacitors, and metal to metal/polysilicon (poly) capacitors. Junction capacitors simply comprise a junction between a p-type semiconductor and an n-type semiconductor. The junction capacitor is therefore similar to a diode, however, typically a much larger area is used. When the junction is reverse biased, the depletion layer forms the dielectric, and the p and n regions on either side form the capacitor plates. The requirement that the junction must always be reverse biased severely limits the interconnection flexibility of the device. Also the width of the depletion layer is voltage dependent, making the capacitance nonlinear. Further drawbacks of junction capacitors include that they are sensitive to process variations, they have a low Q factor, and they have a large temperature coefficient.
MOS capacitors a essentially an expanded gate structure of a MOS transistor. MOS capacitors provide high capacitance per unit area. However, drawbacks of MOS capacitors include that they are nonlinear, they require a DC bias voltage, they have a low break-down voltage, and they only have a medium Q factor.
Metal to metal capacitors typically comprise two metal layers separated by a dielectric. Alternatively, polysilicon may be substituted for metal. A block diagram of a conventional parallel plate capacitor is illustrated in FIG. 1. Metal to metal capacitors provide linear operation, a high Q factor, and a small temperature coefficient. These features make metal to metal capacitors the preferred type of capacitor for many integrated circuit applications. However, metal to metal capacitors have a relatively low capacitance per unit area. Therefore capacitors are often required that take up large areas on an integrated circuit. Such large capacitors can significantly increase the cost of an integrated circuit. The capacitance of a parallel plate capacitor, such as capacitor 100, is provided by the formula. ##EQU1## where .epsilon. is the permittivity of the dielectric material separating the plates, A is the area of the capacitor plates, and d is the distance between the plates. Technological developments have provided substantial reductions in the minimum horizontal spacing in integrated circuits, and substantial further reductions are expected. However, the distance between layers in an integrated circuit has not been comparably reduced. As a result, metal to metal capacitors continue to require large areas to provide desired capacitance values. Further the relative size of conventional capacitors compared to other circuit elements is likely to grow as horizontal spacing continues to be reduced. A further drawback of metal to metal capacitors is that they typically have a large parasitic bottom-plate capacitance due to their large areas. Parasitic bottom-plate capacitance is the undesirable capacitance between the lower plate of the capacitor and the integrated circuit substrate.
It is therefore an object of the present invention to provide a linear capacitor with increased capacitance per unit area and reduced parasitic bottom-plate capacitance.